{
  "id": "cern_rww_1k2_5_1w_180ppm_vishay_ac01",
  "name": "AC01000001201JA100 (CERN library)",
  "category": "passive",
  "family": "CERN Resistors THD",
  "manufacturer": "VISHAY DRALORIC",
  "mpn_pattern": "AC01000001201JA100",
  "description": "Cemented Wirewound Resistor. Imported from the CERN KiCad library (CERN-OHL-P-2.0, (c) CERN); passed PartReel quality gates. Verified-2D part: upstream ships no 3D models. Lifecycle status: None.",
  "parameters": {
    "contacts": "2",
    "case": "LS15.24 L11 x D4.3",
    "value": "1k2",
    "lifecycle": "None"
  },
  "formats": [
    "kicad_mod",
    "kicad_sym"
  ],
  "files": {
    "footprint": "https://partreel.com/library/passive/cern/cern_rww_1k2_5_1w_180ppm_vishay_ac01/cern_rww_1k2_5_1w_180ppm_vishay_ac01.kicad_mod",
    "symbol": "https://partreel.com/library/passive/cern/cern_rww_1k2_5_1w_180ppm_vishay_ac01/cern_rww_1k2_5_1w_180ppm_vishay_ac01.kicad_sym",
    "footprint_svg": "https://partreel.com/library/passive/cern/cern_rww_1k2_5_1w_180ppm_vishay_ac01/cern_rww_1k2_5_1w_180ppm_vishay_ac01.footprint.svg",
    "symbol_svg": "https://partreel.com/library/passive/cern/cern_rww_1k2_5_1w_180ppm_vishay_ac01/cern_rww_1k2_5_1w_180ppm_vishay_ac01.symbol.svg"
  },
  "datasheet": "https://gitlab.com/ohwr/cern-kicad-libs/-/blob/master/SchLib/Resistors.kicad_sym",
  "license": "CERN-OHL-P-2.0",
  "verified": true,
  "tier": "verified-2d",
  "dimensions_source": "cern-kicad-libs@53054c17 (Resistors THD.pretty/RES_VISHAY_AC01.kicad_mod)",
  "keywords": [
    "cern",
    "cemented",
    "wirewound",
    "resistor"
  ],
  "field_reports": {
    "worked": 0,
    "problem": 0
  },
  "provenance": {
    "dimensions_source": "cern-kicad-libs@53054c17 (Resistors THD.pretty/RES_VISHAY_AC01.kicad_mod)",
    "datasheet": "https://gitlab.com/ohwr/cern-kicad-libs/-/blob/master/SchLib/Resistors.kicad_sym",
    "generator_source": "https://github.com/mingyo186/partreel/blob/main/generators/import_cern.py",
    "quality_gates": {
      "gates": [
        "validate_kicad (structure/pads/layers)",
        "KLC drawing rules (silk/fab/courtyard/pin1)",
        "check_overlap (text collisions)",
        "check_render (files/SVG-vs-source/meta completeness)",
        "check_zfight (3D coplanar faces, merged pins)",
        "validate_step (FreeCAD kernel isValid)"
      ],
      "enforcement": "CI runs all gates on every push and blocks deployment on any failure",
      "ci_config": "https://github.com/mingyo186/partreel/blob/main/.github/workflows/deploy.yml"
    },
    "field_reports": {
      "worked": 0,
      "problem": 0
    },
    "origin": "imported",
    "import": {
      "source_repo": "https://gitlab.com/ohwr/cern-kicad-libs",
      "source_commit": "53054c17",
      "source_files": {
        "db": "CERN.sqlite#Resistors THD#RWW_1K2_5%_1W_180PPM_VISHAY_AC01",
        "symbol": "SchLib/Resistors.kicad_sym#Resistor - 5%",
        "footprint": "PcbLib/Resistors THD.pretty/RES_VISHAY_AC01.kicad_mod"
      },
      "attribution": "CERN (kicad-dev@cern.ch), CERN-OHL-P-2.0",
      "import_date": "2026-07-05",
      "modifications": [
        "extracted single symbol from library",
        "stripped dead 3D model reference (upstream ships no 3D)",
        "auto-added courtyard (pads+outline+poly bbox +0.25mm)"
      ]
    }
  },
  "page": "https://partreel.com/p/cern_rww_1k2_5_1w_180ppm_vishay_ac01/",
  "api": "https://partreel.com/api/v1/parts/cern_rww_1k2_5_1w_180ppm_vishay_ac01.json"
}