Cyclone IV E Family, FPGA, 6272 LEs, 179 I/Os, 256-Pin FBGA, Commercial Grade, Speed Grade 8. Imported from the CERN KiCad library (CERN-OHL-P-2.0, (c) CERN); passed PartReel quality gates. Verified-2D part: upstream ships no 3D models.
Verified-2D part (no 3D model upstream)
IO D4 IO E5 IO F5 IO,_(DQS2L/CQ3L)/(DQS2L/CQ3L) B1 IO,_DIFFIO_L1p C2 IO,_DIFFIO_L1n,_(DATA1,ASDO) C1 IO,_VREFB1N0 F3 IO,_DIFFIO_L2p,_(FLASH_nCE,nCSO) D2 IO,_DIFFIO_L2n D1 IO G5 IO,_DIFFIO_L3p F2 IO,_DIFFIO_L3n F1 IO,_DIFFIO_L4p,_(DQS0L/CQ1L,DPCLK0)/(DQS0L/CQ1L,DPCLK0) G2 IO,_DIFFIO_L4n G1 IO,_(DATA0) H2 A IO,_DIFFIO_L5p,_(DQ1L) J2 IO,_DIFFIO_L5n,_(DQ1L) J1 IO J6 IO,_DIFFIO_L6p K6 IO,_DIFFIO_L6n L6 IO,_DIFFIO_L7p K2 IO,_DIFFIO_L7n,_(DQ1L) K1 IO,_DIFFIO_L8p,_(DQS1L/CQ1L#,DPCLK1)/(DQS1L/CQ1L#,DPCLK1) L2 IO,_DIFFIO_L8n,_(DQ1L) L1 IO,_VREFB2N0 L3 IO,_DIFFIO_L9p,_(DQ1L) N2 IO,_DIFFIO_L9n,_(DQ1L) N1 IO,_RUP1,_(DQ1L) K5 IO,_RDN1,_(DQ1L) L4 IO,_(DQS3L/CQ3L#)/(DQS3L/CQ3L#) R1 IO,_DIFFIO_L10p,_(DQ1L) P2 IO,_DIFFIO_L10n,_(DM1L/BWS#1L) P1 B IO,_DIFFIO_B1p N3 IO,_DIFFIO_B1n,_(DM3B/BWS#3B)/(DM5B/BWS#5B) P3 IO,_DIFFIO_B2p,_(DQ3B)/(DQ5B) R3 IO,_DIFFIO_B2n T3 IO,_(DQS1B/CQ1B#,DPCLK2)/(DQS1B/CQ1B#,DPCLK2) T2 IO,_PLL1_CLKOUTp R4 IO,_PLL1_CLKOUTn T4 IO,_DIFFIO_B4p,_(DQ3B)/(DQ5B) N5 IO,_DIFFIO_B4n,_(DQ3B)/(DQ5B) N6 IO,_(DQ3B)/(DQ5B) M6 IO,_VREFB3N0 P6 IO,_DIFFIO_B5p,_(DQS3B/CQ3B#)/(DQS3B/CQ3B#) M7 IO,_DIFFIO_B5n K8 IO,_DIFFIO_B6p,_(DQ3B)/(DQ5B) R5 IO,_DIFFIO_B6n T5 IO,_DIFFIO_B7p,_(DQ3B)/(DQ5B) R6 IO,_DIFFIO_B7n T6 IO,_(DQ3B)/(DQ5B) L7 IO,_DIFFIO_B8p,_(DQ3B)/(DQ5B) R7 IO,_DIFFIO_B8n,_(DQS5B/CQ5B#)/(DQS5B/CQ5B#) T7 IO,_DIFFIO_B9p,_(DQ3B)/(DQ5B) L8 IO,_DIFFIO_B9n,_(DM5B/BWS#5B)/(DM5B/BWS#5B) M8 IO,_DIFFIO_B10p,_(DQ5B)/(DQ5B) N8 IO,_DIFFIO_B10n,_(DQ5B)/(DQ5B) P8 IO,_DIFFIO_B11p R8 IO,_DIFFIO_B11n T8 C IO,_DIFFIO_B12p R9 IO,_DIFFIO_B12n T9 IO,_DIFFIO_B13p K9 IO,_DIFFIO_B13n L9 IO,_DIFFIO_B14p M9 IO,_DIFFIO_B14n,_(DQ5B)/(DQ5B) N9 IO,_DIFFIO_B15p,_(DQ5B)/(DQ5B) R10 IO,_DIFFIO_B15n,_(DQS4B/CQ5B)/(DQS4B/CQ5B) T10 IO,_DIFFIO_B16p,_(DQ5B)/(DQ5B) R11 IO,_DIFFIO_B16n T11 IO,_DIFFIO_B17p,_(DQ5B)/(DQ5B) R12 IO,_DIFFIO_B17n,_(DQ5B)/(DQ5B) T12 IO,_DIFFIO_B18p K10 IO,_DIFFIO_B18n L10 IO,_(DQS2B/CQ3B)/(DQS2B/CQ3B) P9 IO,_VREFB4N0 P11 IO,_DIFFIO_B19p R13 IO,_DIFFIO_B19n,_(DQ5B)/(DQ5B) T13 IO,_RUP2 M10 IO,_RDN2 N11 IO,_DIFFIO_B20p,_(DQ5B)/(DQ5B) T14 IO,_DIFFIO_B20n,_(DQS0B/CQ1B,DPCLK3)/(DQS0B/CQ1B,DPCLK3) T15 IO R14 IO,_DIFFIO_B21p P14 IO,_DIFFIO_B21n L11 IO,_DIFFIO_B22p M11 IO,_DIFFIO_B22n N12 D IO N13 IO M12 IO L12 IO K12 IO,_RUP3,_(DM1R/BWS#1R) N14 IO,_RDN3,_(DQ1R) P15 IO,_DIFFIO_R11n,_(DQS3R/CQ3R#)/(DQS3R/CQ3R#) P16 IO,_DIFFIO_R11p,_(DQ1R) R16 IO K11 IO,_DIFFIO_R10n,_(DQ1R) N16 IO,_DIFFIO_R10p,_(DQ1R) N15 IO,_VREFB5N0 L14 IO,_(DQ1R) L13 IO,_DIFFIO_R9n,_(DQ1R) L16 IO,_DIFFIO_R9p L15 IO J11 IO,_DIFFIO_R8n,_(DQ1R) K16 IO,_DIFFIO_R8p,_(DQS1R/CQ1R#,DPCLK4)/(DQS1R/CQ1R#,DPCLK4) K15 IO,_DIFFIO_R7n,_(DEV_OE) J16 IO,_DIFFIO_R7p,_(DEV_CLRn) J15 IO,_DIFFIO_R6n,_(DQ1R) J14 IO,_DIFFIO_R6p J12 IO,_(DQ1R) J13 E IO,_DIFFIO_R4n,_(INIT_DONE) G16 IO,_DIFFIO_R4p,_(CRC_ERROR) G15 IO F13 IO,_DIFFIO_R3n,_(nCEO) F16 IO,_DIFFIO_R3p,_(CLKUSR) F15 IO,_(DQS0R/CQ1R,DPCLK5)/(DQS0R/CQ1R,DPCLK5) B16 IO,_VREFB6N0 F14 IO,_DIFFIO_R2n D16 IO,_DIFFIO_R2p D15 IO G11 IO,_DIFFIO_R1n,_(DQS2R/CQ3R)/(DQS2R/CQ3R) C16 IO,_DIFFIO_R1p C15 F IO,_DIFFIO_T21n C14 IO,_DIFFIO_T21p,_(DQ5T)/(DQ5T) D14 IO,_DIFFIO_T20n D11 IO,_DIFFIO_T20p,_(DQS0T/CQ1T,DPCLK6)/(DQS0T/CQ1T,DPCLK6) D12 IO,_DIFFIO_T19n A13 IO,_DIFFIO_T19p,_(DQ5T)/(DQ5T) B13 IO,_PLL2_CLKOUTn A14 IO,_PLL2_CLKOUTp B14 IO,_RUP4 E11 IO,_RDN4 E10 IO,_DIFFIO_T18n,_(DQ5T)/(DQ5T) A12 IO,_DIFFIO_T18p,_(DQ5T)/(DQ5T) B12 IO,_DIFFIO_T17n,_(DQ5T)/(DQ5T) A11 IO,_DIFFIO_T17p,_(DQ5T)/(DQ5T) B11 IO,_VREFB7N0 C11 IO,_DIFFIO_T16n F10 IO,_DIFFIO_T16p,_(DQS2T/CQ3T)/(DQS2T/CQ3T) F9 IO,_DIFFIO_T15n F11 IO,_DIFFIO_T15p A15 IO,_DIFFIO_T14n,_(DQ5T)/(DQ5T) A10 IO,_DIFFIO_T14p,_(DQ5T)/(DQ5T) B10 IO,_DIFFIO_T13n,_(DQ5T)/(DQ5T) C9 IO,_DIFFIO_T13p,_(DM5T/BWS#5T)/(DM5T/BWS#5T) D9 IO,_(DQS4T/CQ5T)/(DQS4T/CQ5T) E9 IO,_DIFFIO_T12n A9 IO,_DIFFIO_T12p B9 G IO,_DIFFIO_T11n A8 IO,_DIFFIO_T11p B8 IO,_(DQS5T/CQ5T#)/(DQS5T/CQ5T#) C8 IO,_(DQ3T)/(DQ5T) D8 IO,_DIFFIO_T10n,_(DATA2),_(DQ3T)/(DQ5T) E8 IO,_DIFFIO_T10p,_(DATA3) F8 IO,_DIFFIO_T9n,_(DQ3T)/(DQ5T) A7 IO,_DIFFIO_T9p,_(DATA4),_(DQ3T)/(DQ5T) B7 IO,_DIFFIO_T8n F6 IO,_DIFFIO_T8p F7 IO,_VREFB8N0 C6 IO,_DIFFIO_T7n,_(DQS3T/CQ3T#)/(DQS3T/CQ3T#) A6 IO,_DIFFIO_T7p,_(DQ3T)/(DQ5T) B6 IO,_(DATA5),_(DQ3T)/(DQ5T) E7 IO,_(DATA6),_(DQ3T)/(DQ5T) E6 IO,_DIFFIO_T6n,_(DATA7),_(DQ3T)/(DQ5T) A5 IO,_DIFFIO_T5n A2 IO,_DIFFIO_T5p,_(DQ3T)/(DQ5T) B5 IO,_DIFFIO_T4n,_(DM3T/BWS#3T)/(DM5T/BWS#5T) A4 IO,_DIFFIO_T4p B4 IO,_DIFFIO_T3n D5 IO,_DIFFIO_T3p D6 IO,_DIFFIO_T2n A3 IO,_DIFFIO_T2p,_(DQS1T/CQ1T#,DPCLK7)/(DQS1T/CQ1T#,DPCLK7) B3 IO,_DIFFIO_T1n C3 IO,_DIFFIO_T1p D3 H CLK1,_DIFFCLK_0n E1 CLK2,_DIFFCLK_1p M2 CLK3,_DIFFCLK_1n M1 CLK4,_DIFFCLK_2p E15 CLK5,_DIFFCLK_2n E16 CLK6,_DIFFCLK_3p M15 CLK7,_DIFFCLK_3n M16 I TDI H4 TDO J4 TCK H3 TMS J5 MSEL0 H13 MSEL1 H12 MSEL2 G12 nCE J3 DCLK H1 CONF_DONE H14 nCONFIG H5 nSTATUS F4 J VCCIO1 E3 VCCIO1 G3 VCCIO2 K3 VCCIO2 M3 VCCIO3 P4 VCCIO3 P7 VCCIO3 T1 VCCIO4 P10 VCCIO4 P13 VCCIO4 T16 VCCIO5 K14 VCCIO5 M14 VCCIO6 E14 VCCIO6 G14 VCCIO7 A16 VCCIO7 C10 VCCIO7 C13 VCCIO8 A1 VCCIO8 C4 VCCIO8 C7 VCCINT G6 VCCINT G7 VCCINT G8 VCCINT G9 VCCINT G10 VCCINT H6 VCCINT H11 VCCINT K7 K GND H7 GND H8 GND H9 GND H10 GND J7 GND J8 GND J9 GND J10 GND B2 GND B15 GND C5 GND C12 GND D7 GND D10 GND E4 GND E13 GND G4 GND G13 GND K4 GND K13 GND M4 GND M13 GND N7 GND N10 GND P5 GND P12 GND R2 GND R15 GND E2 GND H16 GND H15 L VCCA1 L5 VCCD_PLL1 N4 VCCA2 F12 VCCD_PLL2 D13 GNDA1 M5 GNDA2 E12 M