Home / CERN Logic / LPC1768FBD100 (CERN library)LPC1768FBD100 (CERN library)
32-bit 100MHz ARM Cortex-M3 Microcontroller, 512kB Flash, 64kB SRAM, with Ethernet, USB 2.0 Host/Device/OTG, CAN. Imported from the CERN KiCad library (CERN-OHL-P-2.0, (c) CERN); passed PartReel quality gates. Verified-2D part: upstream ships no 3D models.
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Verified-2D part (no 3D model upstream)
P0[0]/RD1/TXD3/SDA1 46 P0[1]/TD1/RXD3/SCL1 47 P0[2]/TXD0/AD0[7] 98 P0[3]/RXD0/AD0[6] 99 P0[4]/I2SRX_CLK/RD2/CAP2[0] 81 P0[5]/I2SRX_WS/TD2/CAP2[1] 80 P0[6]/I2SRX_SDA/SSEL1/MAT2[0] 79 P0[7]/I2STX_CLK/SCK1/MAT2[1] 78 P0[8]/I2STX_WS/MISO1/MAT2[2] 77 P0[9]/I2STX_SDA/MOSI1/MAT2[3] 76 P0[10]/TXD2/SDA2/MAT3[0] 48 P0[11]/RXD2/SCL2/MAT3[1] 49 P0[15]/TXD1/SCK0/SCK 62 P0[16]/RXD1/SSEL0/SSEL 63 P0[17]/CTS1/MISO0/MISO 61 P0[18]/DCD1/MOSI0/MOSI 60 P0[19]/DSR1/SDA1 59 P0[20]/DTR1/SCL1 58 P0[21]/RI1/RD1 57 P0[22]/RTS1/TD1 56 P0[23]/AD0[0]/I2SRX_CLK/CAP3[0] 9 P0[24]/AD0[1]/I2SRX_WS/CAP3[1] 8 P0[25]/AD0[2]/I2SRX_SDA/TXD3 7 P0[26]/AD0[3]/AOUT/RXD3 6 P0[27]/SDA0/USB_SDA 25 P0[28]/SCL0/USB_SCL 24 P0[29]/USB_D+ 29 P0[30]/USB_D- 30 P1[0]/ENET_TXD0 95 P1[1]/ENET_TXD1 94 P1[4]/ENET_TX_EN 93 P1[8]/ENET_CRS 92 P1[9]/ENET_RXD0 91 P1[10]/ENET_RXD1 90 P1[14]/ENET_RX_ER 89 P1[15]/ENET_REF_CLK 88 P1[16]/ENET_MDC 87 P1[17]/ENET_MDIO 86 P1[18]/USB_UP_LED/PWM1[1]/CAP1[0] 32 P1[19]/MCOA0/~{USB_PPWR}/CAP1[1] 33 P1[20]/MCI0/PWM1[2]/SCK0 34 P1[21]/~{MCABORT}/PWM1[3]/SSEL0 35 P1[22]/MCOB0/USB_PWRD/MAT1[0] 36 P1[23]/MCI1/PWM1[4]/MISO0 37 P1[24]/MCI2/PWM1[5]/MOSI0 38 P1[25]/MCOA1/MAT1[1] 39 P1[26]/MCOB1/PWM1[6]/CAP0[0] 40 P1[27]/CLKOUT/~{USB_OVRCR}/CAP0[1] 43 P1[28]/MCOA2/PCAP1[0]/MAT0[0] 44 P1[29]/MCOB2/PCAP1[1]/MAT0[1] 45 P1[30]/VBUS/AD0[4] 21 P1[31]/SCK1/AD0[5] 20 P2[0]/PWM1[1]/TXD1 75 P2[1]/PWM1[2]/RXD1 74 P2[2]/PWM1[3]/CTS1/TRACEDATA[3] 73 P2[3]/PWM1[4]/DCD1/TRACEDATA[2] 70 P2[4]/PWM1[5]/DSR1/TRACEDATA[1] 69 P2[5]/PWM1[6]/DTR1/TRACEDATA[0] 68 P2[6]/PCAP1[0]/RI1/TRACECLK 67 P2[7]/RD2/RTS1 66 P2[8]/TD2/TXD2 65 P2[9]/USB_CONNECT/RXD2 64 P2[10]/~{EINT0}/NMI 53 P2[11]/~{EINT1}/I2STX_CLK 52 P2[12]/~{EINT2}/I2STX_WS 51 P2[13]/~{EINT3}/I2STX_SDA 50 P3[25]/MAT0[0]/PWM1[2] 27 P3[26]/STCLK/MAT0[1]/PWM1[3] 26 P4[28]/RX_MCLK/MAT2[0]/TXD3 82 P4[29]/TX_MCLK/MAT2[1]/RXD3 85 NC 13 ~{RESET} 17 ~{RSTOUT} 14 RTCX1 16 RTCX2 18 TDI 2 TDO/SWO 1 TCK/SWDCLK 5 TMS/SWDIO 3 ~{TRST} 4 RTCK 100 XTAL1 22 XTAL2 23 A VDD(3V3) 28 VDD(3V3) 54 VDD(3V3) 71 VDD(3V3) 96 VDD(REG)(3V3) 42 VDD(REG)(3V3) 84 VDDA 10 VREFN 15 VREFP 12 VSS 31 VSS 41 VSS 55 VSS 72 VSS 83 VSS 97 VSSA 11 VBAT 19 B
Specifications
Manufacturer NXP SEMICONDUCTORS Family CERN Logic MPN pattern LPC1768FBD100 Pins 100 Mounting SMD
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Datasheet
Find datasheet (NXP SEMICONDUCTORS LPC1768FBD100) →
Source library file (provenance)
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Affiliate link · Part license: CERN-OHL-P-2.0
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