Home / CERN Logic / PCI9056-BA66BI-G (CERN library)PCI9056-BA66BI-G (CERN library)
32-Bit 66MHz PCI Bus Mastering I/O Accelerator for PowerQUICC and Generic 32-Bit, 66MHz Local Bus Design. Imported from the CERN KiCad library (CERN-OHL-P-2.0, (c) CERN); passed PartReel quality gates. Verified-2D part: upstream ships no 3D models.
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Verified-2D part (no 3D model upstream)
LD0 P16 LD1 M13 LD2 N15 LD3 M14 LD4 L13 LD5 N16 LD6 M15 LD7 L14 LD8 L15 LD9 M16 LD10 L16 LD11 K14 LD12 K15 LD13 K16 LD14 J14 LD15 J15 LD16 J16 LD17 H16 LD18 H15 LD19 H14 LD20 H13 LD21 G16 LD22 G15 LD23 G14 LD24 F16 LD25 E16 LD26 F15 LD27 F14 LD28 E15 LD29 D15 LD30 E14 LD31 C16 LA0 P7 LA1 R7 LA2 T7 LA3 N8 LA4 P8 LA5 R8 LA6 T8 LA7 T9 LA8 R9 LA9 P9 LA10 T10 LA11 R10 LA12 P10 LA13 T11 LA14 N10 LA15 P11 LA16 R11 LA17 T12 LA18 R12 LA19 T13 LA20 N11 LA21 P12 LA22 T14 LA23 R13 LA24 N12 LA25 P13 LA26 T15 LA27 R14 LA28 R15 LA29 N13 LA30 R16 LA31 N14 DP0 D13 DP1 C14 DP2 B16 DP3 D14 ~{TS} D12 ~{BURST} A14 RD/~{WR} P14 ~{TA} C15 ~{BDIP} C12 ~{BR} A16 ~{BG} B14 ~{LINTi} C11 ~{LINTo} B11 ~{LRESET} D11 USERi/~{LLOCKi} A11 ~{TEA} C13 ~{BIGEND}/~{WAIT} A9 ~{BB} A13 ~{RETRY} B13 ~{BI} E13 ~{MDREQ}/DMPAF/~{EOT} A12 USERo/~{LLOCKo} D10 ~{DREQ0} A10 ~{DREQ1} C10 ~{DACK0} C9 ~{DACK1} B10 EECS A8 EESK B8 EEDI/EEDO C8 ~{CCS} B9 MODE1 A15 MODE0 B15 ~{IDDQEN} B7 ~{HOSTEN} B12 TSIZ1 P15 TSIZ0 T16 LCLK D16 TCK B5 TMS A5 TDI D6 ~{TRST} C6 TDO A4 A C/~{BE0} N2 C/~{BE1} K2 C/~{BE2} G3 C/~{BE3} E4 ~{FRAME} G2 ~{IRDY} G1 ~{TRDY} H4 ~{STOP} H2 ~{DEVSEL} H3 IDSEL D3 ~{PERR} J2 ~{SERR} J3 ~{LOCK} H1 PAR K1 ~{REQ0}/~{GNT} D5 ~{REQ1} P4 ~{REQ2} R3 ~{REQ3} P5 ~{REQ4} T4 ~{REQ5} N6 ~{REQ6} R6 ~{GNT0}/~{REQ} A3 ~{GNT1} T2 ~{GNT2} T3 ~{GNT3} N5 ~{GNT4} R4 ~{GNT5} R5 ~{GNT6} T5 ~{INTA} B4 PCLK J1 ~{RST} C5 ~{PME} A6 ~{PMEREQ} C7 AD0 P3 AD1 R2 AD2 R1 AD3 T1 AD4 P2 AD5 M4 AD6 N3 AD7 P1 AD8 M3 AD9 L4 AD10 N1 AD11 M1 AD12 L3 AD13 L2 AD14 L1 AD15 K3 AD16 F1 AD17 F2 AD18 E1 AD19 F3 AD20 D1 AD21 E3 AD22 D2 AD23 C1 AD24 C2 AD25 A1 AD26 B1 AD27 B2 AD28 C3 AD29 D4 AD30 A2 AD31 C4 ~{BD_SEL} B6 CPCISW T6 ~{ENUM} P6 ~{LEDon} N7 B VRING M10 VRING M8 VRING M7 VRING K12 VRING K5 VRING J12 VRING H12 VRING H5 VRING G12 VRING G5 VRING E10 VRING E8 VRING E7 VIO N4 VIO M2 VIO E2 VIO B3 VCORE N9 VCORE K13 VCORE K4 VCORE F13 VCORE F4 VCORE D9 2.5VAUX D7 Card_VAUX A7 PRESENT_DET D8 VSS E5 VSS E6 VSS E9 VSS E11 VSS E12 VSS F5 VSS F6 VSS F7 VSS M12 VSS M11 VSS M9 VSS M6 VSS M5 VSS L12 VSS L11 VSS L10 VSS L9 VSS L8 VSS L7 VSS L6 VSS L5 VSS K11 VSS K10 VSS K9 VSS K8 VSS K7 VSS K6 VSS J13 VSS J11 VSS J10 VSS J9 VSS J8 VSS J7 VSS J6 VSS J5 VSS J4 VSS H11 VSS H10 VSS H9 VSS H8 VSS H7 VSS H6 VSS G13 VSS G11 VSS G10 VSS G9 VSS G8 VSS G7 VSS G6 VSS G4 VSS F12 VSS F11 VSS F10 VSS F9 VSS F8 C
Specifications
Manufacturer PLX TECHNOLOGY Family CERN Logic MPN pattern PCI9056-BA66BI-G Pins 256 Mounting SMD
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Datasheet
Find datasheet (PLX TECHNOLOGY PCI9056-BA66BI-G) →
Source library file (provenance)
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Affiliate link · Part license: CERN-OHL-P-2.0
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For AI agents
Machine-readable data for this part: /api/v1/parts/cern_pci9056_ba66bi_g_m.json (absolute download URLs).
MCP: https://mcp.partreel.com/mcp → get_part("cern_pci9056_ba66bi_g_m"). See /llms.txt · agent guide